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19-4166; Rev 1; 4/09
KIT ATION EVALU ABLE AVAIL
PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN
General Description
The MAX8819_ is a complete power solution for MP3 players and other handheld applications. The IC includes a battery charger, step-down converters, and WLED power. It features an input current-limit switch to power the IC from an AC-to-DC adapter or USB port, a 1-cell lithium ion (Li+) or lithium polymer (Li-Poly) charger, three step-down converters, and a step-up converter with serial step dimming for powering two to six white LEDs. All power switches for charging and switching the system load between battery and external power are included on-chip. No external MOSFETs are required. The MAX8819C offers a sequenced power-up/powerdown of OUT1, OUT2, and then OUT3. Maxim's Smart Power SelectorTM makes the best use of AC-to-DC adapter power or limited USB power. Battery charge current and input current limit are independently set. Input power not used by the system charges the battery. Charge current is resistor programmable and the input current limit can be selected as 100mA, 500mA, or 1A. Automatic input selection switches the system load from battery to external power. In addition, on-chip thermal limiting reduces the battery charge rate to prevent charger overheating. o o o o
Features
Smart Power Selector Operates with No Battery Present USB/AC Adapter One-Cell Li+ Charger Three 2MHz Step-Down Converters 95% Peak Efficiency 100% Duty Cycle 3% Output Accuracy over Load/Line/ Temperature 2 to 6 Series WLED Driver with Dimming Control Active-Low REG1 Reset Output Short-Circuit/Thermal-Overload/Input Undervoltage/Overvoltage Protection Power-Up/Down Sequencing (MAX8819C) Total Solution Size: Less Than 90mm2
MAX8819A/MAX8819B/MAX8819C
o o o o o
Typical Operating Circuit
USB/AC-TO-DC ADAPTER DC DLIM1 DLIM2 BAT + ENABLE SYSTEM ENABLE CHARGER ENABLE BACKLIGHT SYS EN123 CEN EN4 LX4 OVP4 LX2 LX1 OUT1 I/O Li+/Li-Poly BATTERY SYS
Applications
MP3 Players Portable GPS Devices Low-Power Handheld Products Cellular Telephones Digital Cameras Handheld Instrumentation PDAs
MAX8819_
Ordering Information
PART MAX8819AETI+ MAX8819BETI+ MAX8819CETI+ TEMP RANGE PINPACKAGE SYS VOLTAGE (V) 4.35 5.3 4.35
FB4 LX3
OUT2 MEMORY
OUT3 CORE
-40C to +85C 28 TQFN-EP* -40C to +85C 28 TQFN-EP* -40C to +85C 28 TQFN-EP*
CISET CHG RST1 CHG RST1
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
Smart Power Selector is a trademark of Maxim Integrated Products, Inc.
Pin Configuration appears at end of data sheet.
1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN MAX8819A/MAX8819B/MAX8819C
ABSOLUTE MAXIMUM RATINGS
DC, SYS, BAT, CISET, DLIM1, DLIM2, EN123 CEN, EN4, CHG, RST1, FB1, FB2, FB3 to GND....-0.3V to +6V PV2 to GND ...............................................-0.3V to (VSYS + 0.3V) PV13 to SYS...........................................................-0.3V to +0.3V PG1, PG2, PG3, PG4 to GND................................-0.3V to +0.3V COMP4, FB4 to GND ................................-0.3V to (VSYS + 0.3V) LX4 to PG4 .............................................................-0.3V to +33V OVP4 to GND .........................................................-0.3V to +33V LX1, LX2, LX3 Continuous Current (Note 1) .........................1.5A LX4 Current ................................................................750mARMS Output Short-Circuit Duration.....................................Continuous Continuous Power Dissipation (TA = +70C) 28-Pin Thin QFN Single-Layer Board (derate 20.8mW/C above +70C)...........................................................1666.7mW 28-Pin Thin QFN Multilayer Board (derate 28.6mW/C above +70C)...........................................................2285.7mW Junction-to-Case Thermal Resistance (JC) (Note 2) 28-Lead Thin QFN...........................................................3C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature........................................-40C to +125C Storage Temperature.........................................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Note 1: LX1, LX2, LX3 have clamp diodes to their respective PG_ and PV_. Applications that forward bias these diodes must take care not to exceed the package power dissipation limits. Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to http://www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(DC, LX_ unconnected; VEP = VGND = 0V, VBAT = 4V, DLIM[1:2] = 00, EN123 = EN4 = low, VFB1 = VFB2 = VFB3 = 1.1V, VFB4 = 0.6V, PV13 = PV2 = SYS, TA = -40C to +85C, capacitors as shown in Figure 1, RCISET = 3k, unless otherwise noted.) (Note 3)
PARAMETER DC POWER INPUT DC Voltage Range SYS Regulation Voltage DC Undervoltage Threshold DC Overvoltage Threshold DC Current Limit (Note 4) VDC VSYS_REG VUVLO_DC VOVLO_DC IDCLIM VDC = 5.75V MAX8819A/MAX8819C MAX8819B 4.1 4.3 5.1 3.95 5.811 90 450 900 4.35 5.3 4.00 5.9 95 475 1000 0.02 1.33 5.5 4.4 5.5 4.05 6.000 100 500 1100 0.035 mA V V V V SYMBOL CONDITIONS MIN TYP MAX UNITS
VDC rising, 500mV typical hysteresis VDC rising, 300mV typical hysteresis VDC = 5.75V, VSYS = 5V DLIM[1:2] = 10 for MAX8819B or VSYS = DLIM[1:2] = 01 4V for MAX8819A/ DLIM[1:2] = 00 MAX8819C DLIM[1:2] = 11 (suspend) DLIM[1:2] 11, ISYS = 0mA, IBAT = 0mA, EN123 = low, EN4 = low, CEN = high, VDC = 5.5V DLIM[1:2] 11, ISYS = 0mA, EN123 = low, EN4 = low, CEN = low, VDC = 5.5V
DC Quiescent Current
IDCIQ
mA
0.95 0.330 1.5 0.700 ms C %/C
DC-to-SYS Dropout Resistance DC-to-SYS Soft-Start Time DC Thermal-Limit Temperature DC Thermal-Limit Gain SYSTEM System Operating Voltage Range
RDS tSS-D-S
VDC = 4V, ISYS = 400mA, DLIM[1:2] = 01 Die temperature where current limit is reduced Amount of input current reduction above thermal-limit temperature
100 5
VSYS
2.6
5.5
V
2
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN
ELECTRICAL CHARACTERISTICS (continued)
(DC, LX_ unconnected; VEP = VGND = 0V, VBAT = 4V, DLIM[1:2] = 00, EN123 = EN4 = low, VFB1 = VFB2 = VFB3 = 1.1V, VFB4 = 0.6V, PV13 = PV2 = SYS, TA = -40C to +85C, capacitors as shown in Figure 1, RCISET = 3k, unless otherwise noted.) (Note 3)
PARAMETER System Undervoltage Lockout Threshold BAT-to-SYS Reverse Regulation Voltage SYMBOL CONDITIONS MIN 2.45 TYP 2.5 MAX 2.55 UNITS V
MAX8819A/MAX8819B/MAX8819C
VUVLO_SYS VSYS falling, 100mV hysteresis DC and BAT are delivering current to SYS; IBAT = 95mA; VDC = 4.3V, MAX8819A/MAX8819C (only) VDC = 0V, EN123 = low, EN4 = low, VBAT = 4V VDC = 5V, DLIM[1:2] 11, EN123 = low, EN4 = low, VBAT = 4V VDC = 0V, EN123 = high, EN4 = low, VBAT = 4V (step-down converters are not in dropout) VDC = 0V, EN123 = high, EN4 = high, VBAT = 4V (step-down converters are not in dropout)
VBSREG
50
66
90
mV
10 0
20 10 A
Quiescent Current
ISYS + IPV13 + IPV2
128
290
362
730
BATTERY CHARGER (VDC = 5.0V) BAT-to-SYS On-Resistance BAT Regulation Voltage (Figure 2) BAT Recharge Threshold BAT Prequalification Threshold RCISET Resistance Range CISET Voltage VCISET VBATPRQ RBS VBATREG VDC = 0V, VBAT = 4.2V, ISYS = 0.9A TA = +25C TA = -40C to +85C (Note 4) VBAT rising, 180mV hysteresis, Figure 2 Guaranteed by BAT fast-charge current limit RCISET = 7.5k, IBAT = 267mA DLIM[1:2] = 10, RCISET = 3k DLIM[1:2] = 01, RCISET = 3k BAT Fast-Charge Current Limit ICHGMAX DLIM[1:2] = 00, RCISET = 15k DLIM[1:2] = 00, RCISET = 7.5k DLIM[1:2] = 00, RCISET = 3.74k BAT Prequalification Current Top-Off Threshold (Note 5) IPREQUAL ITOPOFF VBAT = 2.5V, RCISET = 3.74k TA = +25C, RCISET = 3.74k VDC = 0V, EN123 = low, EN4 = low, CEN = low, VBAT = 4V VDC = 5V, DLIM[1:2] = 11, EN123 = low, EN4 = low, VBAT = 4V 4.174 4.158 -135 2.9 3 0.9 87 450 170 375 740 60 60 1.0 92 472 200 400 802 82 82 10 0 0.073 4.200 4.200 -100 3.0 0.165 4.221 4.242 -65 3.1 15 1.1 100 500 230 425 860 105 105 20 A mA mA mA V mV V k V
BAT Leakage Current
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN MAX8819A/MAX8819B/MAX8819C
ELECTRICAL CHARACTERISTICS (continued)
(DC, LX_ unconnected; VEP = VGND = 0V, VBAT = 4V, DLIM[1:2] = 00, EN123 = EN4 = low, VFB1 = VFB2 = VFB3 = 1.1V, VFB4 = 0.6V, PV13 = PV2 = SYS, TA = -40C to +85C, capacitors as shown in Figure 1, RCISET = 3k, unless otherwise noted.) (Note 3)
PARAMETER SYMBOL Slew rate Charger Soft-Start Time tSS_CHG Time from 0 to 500mA Time from 0 to 100mA Time from 100mA to 500mA Timer Accuracy Timer Suspend Threshold CISET voltage when the fast-charge timer suspends; 300mV translates to 20% of the maximum fast-charge current limit CISET voltage when the fast-charge timer extends; 750mV translates to 50% of the maximum fast-charge current limit tPREQUAL tFSTCHG tTOPOFF tSS1, tSS2, tSS3 tSS4 CCOMP4 = 0.022F to GND TJ rising 250 300 CONDITIONS MIN TYP 333 1.5 0.3 1.2 +15 350 % mV ms MAX UNITS mA/ms
Timer Extend Threshold Prequalification Time Fast-Charge Time Top-Off Time REG1, REG2, REG3 Soft-Start Time REG4 Soft-Start Time REGULATOR THERMAL SHUTDOWN Thermal Shutdown Temperature Thermal Shutdown Hysteresis
700
750 33 660 33
800
mV min min min
POWER SEQUENCING (Figures 6 and 7) 2.6 5 +165 15 PV13 supplied from SYS L = 4.7H, RLSR = 0.13 (Note 6) MAX8819A/MAX8819B MAX8819C 400 mA 550 600 230 fOSC/3 (Note 7) TA = +25C TA = +85C 0.997 1 VFB1 = 1.01V -50 -5 -10 1 1 190 250 0.565 0.615 0.600 0.650 0.640 0.750 1.01 1.028 VSYS +50 mA mV Hz V V nA % %/D m m A VSYS ms ms C C V
REG1-SYNCHRONOUS STEP-DOWN CONVERTER Input Voltage Maximum Output Current Short-Circuit Current Short-Circuit Detection Threshold Short-Circuit Foldback Frequency FB1 Voltage Output Voltage Range FB1 Leakage Current Load Regulation Line Regulation p-Channel On-Resistance n-Channel On-Resistance p-Channel Current-Limit Threshold
L = 4.7H, RLSR = 0.13
IOUT1 = 100mA to 300mA (Note 9) VPV13 = 4.0V, ILX1 = 180mA VPV13 = 4.0V, ILX1 = 180mA MAX8819A/MAX8819B MAX8819C
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN
ELECTRICAL CHARACTERISTICS (continued)
(DC, LX_ unconnected; VEP = VGND = 0V, VBAT = 4V, DLIM[1:2] = 00, EN123 = EN4 = low, VFB1 = VFB2 = VFB3 = 1.1V, VFB4 = 0.6V, PV13 = PV2 = SYS, TA = -40C to +85C, capacitors as shown in Figure 1, RCISET = 3k, unless otherwise noted.) (Note 3)
PARAMETER Skip-Mode Transition Current n-Channel Zero-Crossing Threshold Maximum Duty Cycle Minimum Duty Cycle PWM Frequency Internal Discharge Resistance in Shutdown Input Voltage Maximum Output Current Short-Circuit Current Short-Circuit Detection Threshold Short-Circuit Foldback Frequency FB2 Voltage Output Voltage Range FB2 Leakage Current Load Regulation Line Regulation p-Channel On-Resistance n-Channel On-Resistance p-Channel Current-Limit Threshold Skip-Mode Transition Current n-Channel Zero-Crossing Threshold Maximum Duty Cycle Minimum Duty Cycle PWM Frequency Internal Discharge Resistance in Shutdown REG2 Disable Input Voltage ISYS fOSC EN123 = low, resistance from LX2 to PG2 VPV2 = 0V, REG2 disabled (Note 10) PV13 supplied from SYS 1.8 100 12.5 2.0 1.0 -25 VSYS 2.2 VFB2 = 1.01V TA = +25C TA = +85C (Note 7) 0.997 1 -50 -5 -50 1 1 290 200 0.512 0.565 0.550 0.600 80 10 0.595 0.700 fOSC EN123 = low, resistance from LX1 to PG1 1.8 100 12.5 2.0 1.0 2.2 SYMBOL (Note 8) CONDITIONS MIN TYP 80 10 MAX UNITS mA mA % % MHz k
MAX8819A/MAX8819B/MAX8819C
REG2-SYNCHRONOUS STEP-DOWN CONVERTER PV2 supplied from SYS L = 4.7H, RLSR = 0.13 (Note 6) MAX8819A/MAX8819B MAX8819C 300 mA 500 600 230 fOSC/3 1.012 1.028 VSYS +50 mA mV Hz V V nA % %/D m m A mA mA % % MHz k A V VSYS V
L = 4.7H, RLSR = 0.13
IOUT2 = 100mA to 300mA (Note 9) VPV2 = 4.0V, ILX2 = 180mA VPV2 = 4.0V, ILX2 = 180mA MAX8819A/MAX8819B MAX8819C (Note 8)
REG3-SYNCHRONOUS STEP-DOWN CONVERTER
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN MAX8819A/MAX8819B/MAX8819C
ELECTRICAL CHARACTERISTICS (continued)
(DC, LX_ unconnected; VEP = VGND = 0V, VBAT = 4V, DLIM[1:2] = 00, EN123 = EN4 = low, VFB1 = VFB2 = VFB3 = 1.1V, VFB4 = 0.6V, PV13 = PV2 = SYS, TA = -40C to +85C, capacitors as shown in Figure 1, RCISET = 3k, unless otherwise noted.) (Note 3)
PARAMETER Maximum Output Current Short-Circuit Current Short-Circuit Detection Threshold Short-Circuit Foldback Frequency FB3 Voltage Output Voltage Range FB3 Leakage Current Load Regulation Line Regulation p-Channel Current-Limit Threshold Skip-Mode Transition Current n-Channel Zero-Crossing Threshold p-Channel On-Resistance n-Channel On-Resistance Maximum Duty Cycle Minimum Duty Cycle PWM Frequency Internal Discharge Resistance in Shutdown REG4-STEP-UP CONVERTER Input Voltage Output Voltage Range FB4 Regulation Voltage FB4 Leakage Switching Frequency Minimum Duty Cycle Maximum Duty Cycle OVP4 Overvoltage Detection OVP4 Input Current OVP4 Leakage Current n-Channel On-Resistance n-Channel Off-Leakage Current n-Channel Current Limit 90 VOVP OVP4 = SYS, EN4 = high REG4 disabled (EN4 = low), OVP4 = SYS VSYS = 4.0V, ILX4 = 200mA VLX4 = 28V -1 555 -1 24 VOUT4 VFB4 No dimming REG4 disabled (EN4 = low) Power supplied from SYS (see Figure 1) 2.4 VSYS 475 -0.050 0.9 500 +0.005 1 5 94 25 4 +0.001 395 +0.001 695 +1 950 +1 26 5.5 24 525 +0.050 1.1 V V mV A MHz % % V A A m A mA fOSC EN123 = low, resistance from LX3 to PG3 1.8 VPV13 = 4.0V, ILX3 = 180mA VPV13 = 4.0V, ILX3 = 180mA 100 12.5 2.0 1.0 2.2 VFB3 = 1.01V TA = +25C TA = +85C (Note 7) 0.997 1 -50 -5 -50 1.3 1 0.512 0.565 0.550 0.600 80 10 290 120 0.595 0.700 SYMBOL L = 4.7H, RLSR = 0.13 (Note 6) CONDITIONS MAX8819A/MAX8819B MAX8819C MIN 300 mA 500 600 230 fOSC/3 1.01 1.028 VSYS +50 mA mV Hz V V nA % %/D A mA mA m m % % MHz k TYP MAX UNITS
L = 4.7H, RLSR = 0.13
IOUT3 = 100mA to 300mA (Note 9) MAX8819A/MAX8819B MAX8819C (Note 8)
6
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN
ELECTRICAL CHARACTERISTICS (continued)
(DC, LX_ unconnected; VEP = VGND = 0V, VBAT = 4V, DLIM[1:2] = 00, EN123 = EN4 = low, VFB1 = VFB2 = VFB3 = 1.1V, VFB4 = 0.6V, PV13 = PV2 = SYS, TA = -40C to +85C, capacitors as shown in Figure 1, RCISET = 3k, unless otherwise noted.) (Note 3)
PARAMETER LED DIMMING CONTROL (EN4) EN4 Low Shutdown Delay EN4 High Enable Delay (Figure 8) EN4 Low Time EN4 High Time RESET (RST1) Reset Trip Threshold Reset Deassert Delay Time Reset Glitch Filter Logic Input-Voltage Low Logic Input-Voltage High Logic Input Pulldown Resistance Logic Leakage Current Logic Output Voltage Low Logic Output-High Leakage Current VTHRST tDRST tGLRST VDC = 4.1V to 5.5V, VSYS = 2.6V to 5.5V VDC = 4.1V to 5.5V, VSYS = 2.6V to 5.5V VLOGIC = 0.4V to 5.5V, CEN, EN123, EN4 VLOGIC = 0 to 5.5V, DLIM1, DLIM2 ISINK = 1mA VLOGIC = 5.5V -1.0 1.2 400 -1.0 760 +0.001 7 +0.001 1200 +1.0 15 +1.0 Voltage from FB1 to GND, VFB1 falling, 50mV hysteresis 0.765 180 0.858 200 50 0.4 0.945 220 V ms s V V k A mV A tSHDN tH_INIT tLO tHI 100 0.5 0.5 500 2 3.2 ms s s s SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX8819A/MAX8819B/MAX8819C
LOGIC (DLIM1, DLIM2, EN123, EN4, CHG, RST1)
Note 3: Limits are 100% production tested at TA = +25C. Limits over the operating temperature range are guaranteed through correlation using statistical quality control (SQC) methods. Note 4: The charger transitions from done to fast-charge mode at this BAT recharge threshold. Note 5: The charger transitions from fast-charge to top-off mode at this top-off threshold (Figure 2). Note 6: The maximum output current is guaranteed by correlation to the p-channel current-limit threshold, p-channel on-resistance, n-channel on-resistance, oscillator frequency, input voltage range, and output voltage range. The parameter is stated for a 4.7H inductor with 0.13 series resistance. See the Step-Down Converter Maximum Output Current section for more information. Note 7: The step-down output voltages are 1% high with no load due to the load-line architecture. Note 8: The skip-mode current threshold is the transition point between fixed-frequency PWM operation and skip-mode operation. The specification is given in terms of output load current for inductor values shown in the typical application circuit (Figure 1). Note 9: Line regulation for the step-down converters is measured as VOUT/D, where D is the duty cycle (approximately VOUT/VIN). Note 10: REG2 is disabled by connecting PV2 to ground, decreasing the quiescent current.
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN MAX8819A/MAX8819B/MAX8819C
Typical Operating Characteristics
(Circuit of Figure 1, TA = +25C, unless otherwise noted.)
DC QUIESCENT CURRENT vs. DC VOLTAGE (CHARGER ENABLED)
MAX8819A toc01
DC QUIESCENT CURRENT vs. DC VOLTAGE (CHARGER DISABLED)
MAX8819A toc02
BATTERY LEAKAGE CURRENT vs. BATTERY VOLTAGE
900 BATTERY LEAKAGE CURRENT (nA) 800 700 600 500 400 300 200 100 VDC = 5V EN123 = 1
MAX8819A toc03
1.2 1.0 QUIESCENT CURRENT (mA) RISING 0.8 0.6 FALLING 0.4 0.2 0 0 1 2 3 4 DC VOLTAGE (V) 5 6
1.2 1.0 QUIESCENT CURRENT (mA) 0.8 0.6 FALLING 0.4 0.2 0 0 1 2 3 4 DC VOLTAGE, VDC (V) 5 6 RISING
1000
0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 BATTERY VOLTAGE (V)
BATTERY LEAKAGE CURRENT vs. BATTERY VOLTAGE
900 BATTERY LEAKAGE CURRENT (nA) 800 700 600 500 400 300 200 100 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 BATTERY VOLTAGE (V) VDC = 0V EN123 = 0
MAX8819A toc04
CHARGE CURRENT vs. BATTERY VOLTAGE
MAX8819A toc05
BATTERY REGULATION VOLTAGE vs. TEMPERATURE
4.24 BATTERY REGULATION VOLTAGE (V) 4.23 4.22 4.21 4.20 4.19 4.18 4.17 4.16 4.15
MAX8819A toc06
1000
500 450 400 CHARGE CURRENT (mA) 350 300 250 200 150 100 50 0 0 1 2 3 BATTERY VOLTAGE (V) 4 5 RCISET = 15k RCISET = 6.8k
4.25
-40
-15
10 35 TEMPERATURE (C)
60
85
SYSTEM VOLTAGE vs. SYSTEM CURRENT
MAX8819A toc07
SYSTEM VOLTAGE vs. SYSTEM CURRENT
VDC = 5.1V VBATT = 4V DLIM[1:2] = 10
MAX8819A toc08
4.02 4.00 SYSTEM VOLTAGE (V) 3.98 3.96 3.94 3.92 3.90 3.88 DC UNCONNECTED VBATT = 4V
4.5 4.4 SYSTEM VOLTAGE (V) 4.3 4.2 4.1 4.0 3.9 3.8
0 100 200 300 400 500 600 700 800 900 1000 OUTPUT CURRENT (mA)
0 100 200 300 400 500 600 700 800 900 1000 OUTPUT CURRENT (mA)
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25C, unless otherwise noted.)
SYSTEM VOLTAGE vs. SYSTEM CURRENT
MAX8819A toc09
MAX8819A/MAX8819B/MAX8819C
AC-TO-DC ADAPTER CONNECT
MAX8819A toc10
4.5 4.4 SYSTEM VOLTAGE (V) 4.3 4.2 4.1 4.0 3.9 3.8 VDC = 5.1V VBATT = 4V DLIM[1:2] = 01
VDC VSYS IDC 3.84V CDC CHARGING 4.3V 4V
5V/div 2V/div
CSYS CHARGING 1A NEGATIVE BATTERY CURRENT FLOWS INTO THE BATTERY 1A/div
IBAT BATTERY CHARGER SOFT-START
1A/div
-1A
0 100 200 300 400 500 600 700 800 900 1000 OUTPUT CURRENT (mA)
400s/div
POWER-UP SEQUENCING (MAX8819A/MAX8819B)
MAX8819A toc11
POWER-UP SEQUENCING (MAX8819C)
MAX8819A toc12
VEN123
2V/div 0V VV3
2V/div 0V 2V/div
VV1
2V/div 0V VV2
0V 2V/div
VV2 VV3
2V/div 0V 2V/div 0V
VV1
0V
2ms/div
1ms/div
POWER-DOWN SEQUENCING (MAX8819C)
MAX8819A toc13
REG1 EFFICIENCY vs. LOAD CURRENT (VREG1 = 3.01V)
90 2V/div 0V 2V/div 0V 80 REG1 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.1 1 10 100 LOAD CURRENT (mA) 1000
MAX8819A toc14
VV3
IV3 = 200mA IV2 = 180mA IV1 = 220mA
100
VV2 VV1 VRST1
2V/div 0V 2V/div 0V
100s/div
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN MAX8819A/MAX8819B/MAX8819C
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25C, unless otherwise noted.)
REG1 LOAD REGULATION
MAX8819A toc15
REG1 DROPOUT VOLTAGE vs. LOAD CURRENT
VOUT1 = 3V 200 DROPOUT VOLTAGE (mV) SYS IS 100mV BELOW THE REG1 NOMINAL REGULATION VOLTAGE
MAX8819A toc16 MAX8819A toc18
3.09 3.08 REG1 OUTPUT VOLTAGE (V) 3.07 3.06 3.05 3.04 3.03 3.02 3.01 3.00 2.99 0 50
250
150
VOUT1 = 3.3V
100
50
0 100 150 200 250 300 350 400 REG1 LOAD CURRENT (mA) 0 50 100 150 200 250 300 350 400 450 OUTPUT CURRENT (mA)
REG1 LIGHT-LOAD SWITCHING WAVEFORMS
MAX8819A toc17
REG1 HEAVY-LOAD SWITCHING WAVEFORMS
VOUT1
20mV/div AC-COUPLED
VOUT1
20mV/div AC-COUPLED
VLX1
2V/div 0V 100mA/div 0mA 20mA LOAD 2s/div
VLX1
2V/div 0V
ILX1 200mA LOAD 400ns/div
ILX1
200mA/div 0mA
LINE TRANSIENT
MAX8819A toc19
REG1 LOAD TRANSIENT (VOUT = 3V)
MAX8819A toc20
300mA 5V VSYS 4V 4V 100mA/div 2V/div IOUT1 VOUT1 VOUT1 VOUT1 = 3V IOUT1 = 30mA 100s/div 200s/div 50mV/div AC-COUPLED 30mA 30mA
100mV/div 3V DC OFFSET
10
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25C, unless otherwise noted.)
REG2 EFFICIENCY vs. LOAD CURRENT (VREG2 = 1.82V)
MAX8819A toc21
MAX8819A/MAX8819B/MAX8819C
REG2 LOAD REGULATION
MAX8819A toc22
REG3 EFFICIENCY vs. LOAD CURRENT (VREG3 = 1.21V)
90 80 REG3 EFFICIENCY (%) 70 60 50 40 30 20 10
MAX8819A toc23
100 90 80 REG2 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.1 1 10 100 LOAD CURRENT (mA)
1.86 1.85 REG2 OUTPUT VOLTAGE (V) 1.84 1.83 1.82 1.81 1.80
100
0 0 50 100 150 200 250 300 350 400 REG2 LOAD CURRENT (mA) 0.1 1 10 100 LOAD CURRENT (mA) 1000
1000
REG3 LOAD REGULATION
1.220 REG3 OUTPUT VOLTAGE (V) 1.215 1.210 1.205 1.200 1.195 1.190 ILX3 VLX3
MAX8819A toc24
REG3 LIGHT-LOAD SWITCHING WAVEFORMS
MAX8819A toc25
1.225
VOUT3
20mV/div AC-COUPLED
2V/div 0V 100mA/div 0mA 20mA LOAD
1.185 0 50 100 150 200 250 300 350 400 REG3 LOAD CURRENT (mA) 2s/div
REG3 HEAVY-LOAD SWITCHING WAVEFORMS
MAX8819A toc26
REG3 LOAD TRANSIENT
MAX8819A toc27
320mA
VOUT3
20mV/div AC-COUPLED
30mA 30mA
100mA/div
VLX3
2V/div 0V
IOUT3 VOUT3
100mV/div 1.2V DC OFFSET
ILX3
200mA/div 0mA 200mA LOAD 400ns/div
200s/div
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN MAX8819A/MAX8819B/MAX8819C
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25C, unless otherwise noted.)
LED EFFICIENCY vs. LED CURRENT (6 LEDS)
MAX8819A toc28
LED EFFICIENCY vs. SYS VOLTAGE
100 95 90 LED EFFICIENCY (%) 85 80 75 70 65 60 55 50 2.5 3.0 3.5 4.0 4.5 SYS VOLTAGE (V) 5.0 5.5 ILED = 25mA INDUCTOR: TOKO 1096AS-100M DIODE: NXP PMEG3005EB 4 LEDS 6 LEDS 100 90 80 LED EFFICIENCY (%) 70 60 50 40 30 20 10 0 0
VSYS = 3.6V 5 10 15 LED CURRENT (mA) 20 25
LED EFFICIENCY vs. LED CURRENT (4 LEDS)
MAX8819A toc30
LED AND BOOST EFFICIENCY vs. SYS VOLTAGE
95 90 85 EFFICIENCY (%) 80 75 70 65 60 LED ILED = 25mA 6 LEDS INDUCTOR: TOKO 1096AS-100M DIODE: NXP PMEG3005EB 2.5 3.0 3.5 4.0 4.5 SYS VOLTAGE (V) 5.0 5.5 BOOST
MAX8819A toc31
REG4 INPUT CURRENT vs. SYS VOLTAGE
MAX8819A toc32
100 90 80 LED EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 5 10 15 LED CURRENT (mA) 20 VSYS = 3.6V
100
300 250 REG4 INPUT CURRENT (mA) 200 150 100 50 6 LEDS, ILED = 25mA 0 2.5 3.0 3.5 4.0 4.5 SYS VOLTAGE (V) 5.0
55 50 25
MAX8819A toc29
5.5
REG4 STARTUP AND SHUTDOWN RESPONSE
MAX8819A toc33
FB4 VOLTAGE vs. LED CURRENT
2V/div 450 400
MAX8819A toc34
500
VEN4
VOVP4
10V/div 0V
FB4 VOLTAGE (mV)
350 300 250 200 150 100
ILED
10mA/div 0mA
50 0 0 5 10 15 LED CURRENT (mA) 20 25
2ms/div
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25C, unless otherwise noted.)
MAXIMUM LED CURRENT vs. TEMPERATURE
25.4 25.3 LED CURRENT (mA) 25.2 25.1 25.0 24.9 24.8 24.7 24.6 24.5 -40 -15 10 35 TEMPERATURE (C) 60 85 0.730 -40 -15 10 35 TEMPERATURE (C) 60 85
MAX8819A toc35
MAX8819A/MAX8819B/MAX8819C
MINIMUM LED CURRENT vs. TEMPERATURE
MAX8819A toc36
25.5
0.750
0.745 LED CURRENT (mA)
0.740
0.735
Pin Description
PIN 1 2 3 4 5 6 7 8 NAME COMP4 FB4 OVP4 PG4 LX4 GND EN4 RST1 External Compensation Capacitor for REG4 REG4 Feedback Input Overvoltage Protection Node for REG4 REG4 Power Ground Inductor Switching Node for REG4 Analog Ground REG4 Enable Input and Dimming Control Digital Input Active-Low, Open-Drain Reset Output. RST1 pulls low to indicate that FB1 is below its regulation threshold. RST1 goes high 200ms after FB1 reaches its regulation threshold. RST1 is high-impedance when EN123 is low, and DC is unconnected. Positive Battery Terminal Connection. Connect BAT to the positive terminal of a single-cell Li+/Li-Poly battery. Bypass BAT to GND with a 4.7F ceramic capacitor. System Supply Output. Bypass SYS to GND with a 10F ceramic capacitor. When a valid voltage is present at DC and DLIM[1:2] 11, VSYS is limited to 4.35V (MAX8819A/MAX8819C) or 5.3V (MAX8819B). When the system load (ISYS) exceeds the input current limit, VSYS drops 75mV (VBSREG) below VBAT, allowing both the external power source and the battery to service SYS. SYS is connected to BAT through an internal 70m system load switch when a valid source is not present at DC. DC Power Input. DC is capable of delivering 1A to SYS. DC supports both AC adapters and USB inputs. As shown in Table 1, the DC current limit is controlled by DLIM1 and DLIM2. Battery Charger Enable Input Feedback Input for REG1. Connect FB1 to the center of a resistor voltage-divider from the REG1 output capacitors to GND to set the output voltage from 1V to VSYS. FUNCTION
9
BAT
10
SYS
11 12 13
DC CEN FB1
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN MAX8819A/MAX8819B/MAX8819C
Pin Description (continued)
PIN 14 15 16 17 18 19 20 21 NAME CISET CHG PG1 LX1 PV13 LX3 PG3 DLIM1 FUNCTION Charge Rate Select Input. Connect a resistor from CISET to GND (RCISET) to set the fast-charge current limit, prequalification-charge current limit, and top-off threshold. Active-Low, Open-Drain Charge Status Output. CHG pulls low to indicate that the battery is charging. See Figure 3 for more information. REG1 Power Ground Inductor Switching Node for REG1. When enabled, LX1 switches between PV13 and PG1 to regulate the FB1 voltage to 1.0V. When disabled, LX1 is pulled to PG1 by 1k in shutdown. Power Input for the REG1 and REG3 Converters. Connect PV13 to SYS. Bypass PV13 to PG1 with a 4.7F ceramic capacitor. Inductor Switching Node for REG3. When enabled, LX3 switches between PV13 and PG3 to regulate the FB3 voltage to 1.0V. When disabled, LX3 is pulled to PG3 by a 1k internal resistor. REG3 Power Ground Input Current-Limit Selection Digital Input 1. Drive high or low according to Table 1 to set the DC input current limit. Feedback Input for REG2. Connect FB2 to the center of a resistor voltage-divider from the REG2 output capacitors to GND to set the output voltage from 1V to VSYS. FB2 must be connected to GND if REG2 is disabled by grounding PV2. Feedback Input for REG3. Connect FB3 to the center of a resistor voltage-divider from the REG3 output capacitors to GND to set the output voltage from 1V to VSYS. REG1, REG2, and REG3 Enable Input. Drive EN123 high to enable REG1, REG2, and REG3. Drive EN123 low to disable REG1, REG2, and REG3. The enable/disable sequencing is shown in Figures 6 and 7. Power Input for REG2. Connect PV2 to SYS for normal operation. Bypass PV2 to PG2 with a 2.2F ceramic capacitor. For systems that do not require REG2, connect PV2, FB2, and PG2 to GND (LX2 may be unconnected or connected to GND). Inductor Switching Node for REG2. When enabled, LX2 switches between PV2 and PG2 to regulate the FB2 voltage to 1.0V. When disabled, LX2 is pulled to PG2 by a 1k internal resistor. REG2 Power Ground Input Current-Limit Selection Digital Input 2. Drive high or low according to Table 1 to set the DC input current limit. Exposed Pad
22
FB2
23 24
FB3 EN123
25
PV2
26 27 28 --
LX2 PG2 DLIM2 EP
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN MAX8819A/MAX8819B/MAX8819C
AC-TO-DC ADAPTER DC C1 4.7F SMART POWER SELECTOR GLITCH FILTER Li+/Li-Poly BATTERY CHARGER AND SYSTEM LOAD SWITCH SYS C5 10F SYS FASTBATTERY DESIRED CAPACITY CHARGE R7 (k) CHARGE CURRENT (mAh) RATE (C) (mA) 300 14.3 210 0.7 0.7 400 280 10.7 0.7 600 7.15 420 560 800 0.7 5.36 0.7 900 632 4.75 ON R2 OUT1 R6 470k CHG OFF
DLIM1 DLIM2 DC ILIM (mA) 1000 0 0 1 0 475 0 1 95 1 SUSPEND 1
BAT C6 + 4.7F CEN CISET Li+/LiPo BATTERY
DLIM1 DLIM2
CHG BIAS MAX8819A MAX8819B MAX8819C
PV13
PV13 C7 4.7F
SYS
ON OFF
EN123
EN REG1 STEP-DOWN DC-DC PWM LX1 FB1 PG1
PG1 L1 4.7H R8 200k C8* 10F PG1 R9 PG1 100k
3.0V 400mA OUT1
L4 10H SYS C2 0.1F PG4 OUT4 C3 0.1F 50V X7R D1 PG4 D2 D3 D4 D5 D7
OUT1 R10 470k RST1
LX4 OVP4 PG4 PG4 COMP4 C4 0.022F REG4 STEP-UP DC-DC EN REG2 STEP-DOWN DC-DC PWM D6 FB4 PV13 LX2 FB2 PG2 REG1/RESET 87% FALLING 50us BLANKING 92% RISING 80ms DELAY RST1
PV2 C9 2.2F PG2 L2 4.7H R12 80.6k
SYS
UP TO 6 WLED
1.8V 200mA C10* 10F PG2 OUT2
PG2 EN REG3 STEP-DOWN DC-DC PWM LX3 FB3 PG3
R13 100k L3 4.7H R14 20.0k C11* 10F PG3 1.2V 300mA OUT3
R1 20 (25mA)
ON OFF
EN4
PULSE DIMMING
GND
EP
R15 PG3 100k *22F FOR MAX8819C IS RECOMMENDED.
Figure 1. Functional Diagram/Typical Applications Circuit
Detailed Description
The MAX8819_ is a complete power solution that includes a battery charger, step-down converters, and WLED power. As shown in Figure 1, the IC integrates a DC power input, Li+/Li-Poly battery charger, three stepdown converters, and one step-up converter for powering
white LEDs. All three step-down converters feature adjustable output voltages set with external resistors. The MAX8819_ has one external power input that connects to either an AC-to-DC adapter or USB port. Logic inputs DLIM1 and DLIM2 select the desired input current limit.
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN MAX8819A/MAX8819B/MAX8819C
In addition to charging the battery, the IC supplies power to the system through the SYS output. The charging current is provided from SYS so that the set input current limit controls the total SYS current, this is the sum of the system load current and the batterycharging current. In some instances, there may not be enough DC input current to supply peak system loads. The Smart Power Selector circuitry offers flexible power distribution from an AC-to-DC adapter or USB source to the battery and system load. The battery is charged with any available power not used by the system load. If a system load peak exceeds the input current limit, supplemental current is taken from the battery. Thermal limiting prevents overheating by reducing power drawn from the input source. In the past, it might have been necessary to reduce system functionality to limit current drain when a USB source is connected. However, with the MAX8819_, this is no longer the case. When the DC or USB source hits its limit, the battery supplies supplemental current to maintain the load. The IC features overvoltage protection. Part of this protection is a 4.35V (MAX8819A/MAX8819C) or 5.3V (MAX8819B) voltage limiter at SYS. If DC exceeds the overvoltage threshold of 5.88V (VOVLO_DC), the input limiter disconnects SYS from DC, but battery-powered operation of all regulators is still allowed. A thermal-limiting circuit reduces the battery charge rate and external power source current to prevent the MAX8819_ from overheating.
System Load Switch An internal 70m MOSFET connects SYS to BAT when no voltage source is available at DC. When an external source is detected at DC, this switch opens and SYS is powered from the valid input source through the Smart Power Selector. When the system load requirements exceed the input current limit, the battery supplies supplemental current to the load through the internal system load switch. If the system load continuously exceeds the input current limit, the battery does not charge, even though external power is connected. This is not expected to occur in most cases because high loads usually occur only in short peaks. During these peaks, battery energy is used, but at all other times the battery charges. DC Power Input (DC, DLIM1, DLIM2) DC is a current-limited power input that supplies the system (SYS) up to 1A. The DC to SYS switch is a linear regulator designed to operate in dropout. This linear regulator prevents the SYS voltage from exceeding 5.3V for the MAX8819B or 4.35V for the MAX8819A/ MAX8819C. As shown in Table 1, DC supports four different current limits that are set with the DLIM1 and DLIM2 digital inputs. These current limits are ideally suited for use with AC-to-DC wall adapters and USB power. The operating voltage range for DC is 4.1V to 5.5V, but it can tolerate up to 6V without damage. When the DC input voltage is below the undervoltage threshold (4V), it is considered invalid. When the DC voltage is below the battery voltage it is considered invalid. The DC power input is disconnected when the DC voltage is invalid. Bypass DC to ground with at least a 4.7F capacitor. Four current settings are provided based upon the settings of DLIM1 and DLIM2, see Table 1. DLIM1 and DLIM2 are deglitched. This deglitching prevents the problem of major carry transitions momentarily entering the suspend state.
Input Limiter
The Smart Power Selector seamlessly distributes power between the current-limited external input (DC), the battery (BAT), and the system load (SYS). The basic functions performed are: With both an external power supply (DC) and battery (BAT) connected: * When the system load requirements are less than the input current limit, the battery is charged with residual power from the input. * When the system load requirements exceed the input current limit, the battery supplies supplemental current to the load through the internal system load switch. * When the battery is connected and there is no external power input, the system (SYS) is powered from the battery. * When an external power input is connected and there is no battery, the system (SYS) is powered from the external power input.
Table 1. DC Current-Limit Settings
DLIM1 0 0 1 1 DLIM2 0 1 0 1 DC ILIM (mA) 1000 475 95 Suspend
16
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN MAX8819A/MAX8819B/MAX8819C
TOP-OFF PREQUALIFICATION FAST-CHARGE (CONSTANT CURRENT) FAST-CHARGE (CONSTANT VOLTAGE) DONE
VBATREG
BATTERY VOLTAGE BATTERY CHARGE CURRENT
VBATPRQ
ICHGMAX
IPREQUAL
ITOPOFF 0
HIGH IMPEDANCE CHG
LOW
Figure 2. Li+/Li-Poly Charge Profile
Battery Charger
Figure 2 shows the typical Li+/Li-Poly charge profile for the MAX8819_, and Figure 3 shows the battery charger state diagram. With a valid DC input that is not suspended, the battery charger initiates a charge cycle once CEN is driven high. It first detects the battery voltage. If the battery
voltage is less than the prequalification threshold (3.0V), the charger enters prequalification mode and charges the battery at 10% of the maximum fast-charge current while deeply discharged. Once the battery voltage rises to 3.0V, the charger transitions to fast-charge mode and applies the maximum charge current. As charging continues, the battery voltage rises until it approaches the battery regulation voltage (4.2V typ)
17
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN MAX8819A/MAX8819B/MAX8819C
ICHGMAX = 2000 x 1.5V RCISET NO INPUT POWER ICHG = 0mA CHG = 1 DC = INVALID
DC = VALID DLIM[1:2] = 11
ANY STATE
INPUT SUSPENDED DLIM[1:2] = 11 ICHG = 0mA CHG = 1
DLIM[1:2] 11
CHARGER DISABLED ICHG = 0mA CHG = 1 CEN = 1 IC SETS TIMER = 0 t > tPREQUAL PREQUALIFICATION ICHG ICHGMAX/10 CHG = 0
CEN = 0
TIMER FAULT ICHG = 0mA CHG = 2Hz SQUAREWAVE
VBAT < 2.82V IC SETS TIMER = 0
VBAT > 3V, IC SETS TIMER = 0
t > tFSTCHG ICHG < ICHGMAX x 53% OR VBAT = VBATREG IC RESUMES TIMER
ICHG < ICHGMAX x 50% AND VBAT < VBATREG IC EXTENDS TIMER BY 2x FAST-CHARGE ICHG ICHGMAX CHG = 0
TIMER EXTEND (ICHGMAX x 20%) < ICHG < (ICHGMAX x 50%) CHG = 0
ICHG < ICHGMAX x 20% IC SETS TIMER = 0
ICHG < ICHGMAX x 10% AND VBAT IC SETS TIMER = 0
TOP-OFF CHG = 1 VBAT = VBATREG ICHG ICHGMAX/10 tTOP-OFF > 33min
ICHG < ISET x 23% OR VBAT = VBATREG ICHG < ICHGMAX x 20% IC RESUMES TIMER AND VBATVBAT < (VBATREG 100mV) IC SETS TIMER = 0
DONE (VBATREG -100mV) VBAT VBATREG ICHG = 0mA CHG = 1
Figure 3. Li+/Li-Poly Charger State Diagram
where charge current starts tapering down. When charge current decreases to 10% of the maximum fastcharge current, the charger enters a 33min top-off state and then charging stops. If the battery voltage subsequently drops 100mV below the battery regulation voltage, charging restarts and the timers reset. The battery charge rate is set by several factors:
18
* Battery voltage * * * * DC input current limit The charge-setting resistor, RCISET The system load (ISYS) The die temperature
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN
* The battery charger is enabled by the processor driving the CEN input high. A valid input must be available at DC. The battery charger is disabled without a valid input at DC or by driving CEN low. * The system current has priority over the battery charger; the battery charger automatically reduces its charge current to maintain the input current limit while still providing the system current (ISYS). * The input current limit is tapered down from full current to zero current when the die temperature transitions from +100C to +120C. Since ISYS has priority over the battery charge current, the battery charge current tapers down before ISYS. The overall result is self-regulation of die temperature (see the Thermal Limiting and Overload Protection section for more information). * The battery charger stops charging in done mode as shown in Figures 2 and 3.
MAX8819A/MAX8819B/MAX8819C
FAST-CHARGE, PREQUALIFICATION, AND TOP-OFF CURRENT vs. CHARGE-SETTING RESISTOR
10,000
1000 CURRENT (mA)
ICHGMAX
100 IPREQUAL, ITOP-OFF 10
1 0 5 10 RCISET (k) 15 20
Figure 4. Calculated Charge Currents vs. RCISET
Charge Status Output (CHG) CHG is an open-drain, active-low output that indicates charger status. As shown in Figures 2 and 3, CHG is low when the charger is in its prequalification or fastcharge states. When a timer count is exceeded in either state, CHG indicates the fault by blinking at a 2Hz rate and remains in that state until the charger is reset by CEN going low, removal of DC or setting DLIM[1:2] = 11.
When the MAX8819_ is used with a microprocessor (P), connect a pullup resistor between CHG and the system logic voltage to indicate charge status to the P. Alternatively, CHG sinks up to 20mA for an LED charge indicator. If the charge status output feature is not required, connect CHG to ground or leave unconnected.
Table 2. Calculated Charge Currents vs. RCISET
RCISET (k) 3.01 4.02 4.99 6.04 6.98 8.06 9.09 10 11 12.1 13 14 15 ICHGMAX (mA) 1000 746 601 497 430 372 330 300 273 248 231 214 200 IPREQUAL (mA) 100 75 60 50 43 37 33 30 27 25 23 21 20 ITOP-OFF (mA) 100 75 60 50 43 37 33 30 27 25 23 21 20
Charge Timer As shown in Figure 3, a fault timer prevents the battery from charging indefinitely. In prequalification mode, the charge time is internally fixed to 33min. tPREQUAL = 33min In fast-charge mode, the charge timer is internally fixed to 660min. tFSTCHG = 660min When the charger exits fast-charge mode, a fixed 33min top-off mode is entered: tTOP-OFF = 33min While in the constant-current fast-charge mode (Figure 2), if the MAX8819_ reduces the battery charge current due to its internal die temperature or large system loads, it slows down the charge timer. This feature eliminates
nuisance charge timer faults. When the battery charge current is between 100% and 50% of its programmed fast-charge level, the fast-charge timer runs at full speed. When the battery charge current is between 50% and 20% programmed fast-charge level, the fastcharge timer is slowed by 2x. Similarly, when the battery charge current is below 20% of the programmed fast-charge level, the fast-charge timer is paused. The fast-charge timer is not slowed or paused when the charger is in the constant voltage portion of its fastcharge mode (Figure 2) where the charge current reduces normally.
19
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN MAX8819A/MAX8819B/MAX8819C
Charge Current (CISET) As shown in Table 2 and Figure 4, a resistor from CISET to ground (RCISET) sets the maximum fast-charge current (ICHGMAX), the charge current in prequalification mode (IPREQUAL), and the top-off threshold (ITOP-OFF). The MAX8819_ supports values of ICHGMAX from 200mA to 1000mA. Select the RCISET as follows:
RCISET = 2000 x 1.5V ICHGMAX The IC uses external resistor-dividers to set the stepdown output voltages between 1V and VSYS. Use at least 10A of bias current in these dividers to ensure no change in the stability of the closed-loop system. To set the output voltage, select a value for the resistor connected between FB_ and GND (R FBL ). The recommended value is 100k. Next, calculate the value of the resistor connected from FB_ to the output (RFBH): V RFBH = RFBL x OUT - 1 1.0V REG1, REG2, and REG3 are optimized for high, medium, and low output voltages, respectively. The highest overall efficiency occurs with V1 set to the highest output voltage and V3 set to the lowest output voltage.
Determine ICHGMAX by considering the characteristics of the battery. It is not necessary to limit the charge current based on the capabilities of the expected AC-toDC adapter or USB/DC input current limit, the system load, or thermal limitations of the PCB. The IC automatically lowers the charging current as necessary to accommodate for these factors. For the selected value of RCISET, calculate ICHGMAX, IPREQUAL, and ITOP-OFF as follows: ICHGMAX = 2000 x 1.5V RCISET
Step-Down Control Scheme At light load, the step-down converter switches only as needed to supply the load. This improves light-load efficiency. At higher load currents (~80mA), the step-down converter transitions to fixed 2MHz switching. Step-Down Dropout and Minimum Duty Cycle All of the step-down regulators are capable of operating in 100% duty-cycle dropout, however, REG1 has been optimized for this mode of operation. During 100% duty-cycle operation, the high-side p-channel MOSFET turns on constantly, connecting the input to the output through the inductor. The dropout voltage (VDO) is calculated as follows:
VDO = ILOAD (RP + RLSR ) where: RP = p-channel power switch RDS(ON) RLSR = external inductor ESR The minimum duty cycle for all step-down regulators is 12.5% (typ), allowing a regulation voltage as low as 1V over the full SYS operating range. REG3 is optimized for low duty-cycle operation.
IPREQUAL = ITOP - OFF = 10% x ICHGMAX
Step-Down Converters (REG1, REG2, REG3)
REG1, REG2, and REG3 are high-efficiency, 2MHz current-mode step-down converters with adjustable outputs. REG1 is designed to deliver 400mA for the MAX8819A/ MAX8819B and 550mA for the MAX8819C. REG2 and REG3 are designed to deliver 300mA for the MAX8819A/ MAX8819B and 500mA for the MAX8819C. The PV13 step-down regulator power input must be connected to SYS. PV2 must also be connected to SYS for normal operation of REG2, but REG2 can be disabled by connecting PV2, FB2, and PG2 to GND. When REG2 is disabled, LX2 can be unconencted or connected to GND. The step-down regulators operate with VSYS from 2.6V to 5.5V. Undervoltage lockout ensures that the step-down regulators do not operate with SYS below 2.55V (max). See the Step-Down Converter Enable/Disable (EN123) and Sequencing section for how to enable and disable the step-down converters. When enabled, the MAX8819_ gradually ramps each output up during a 2.6ms soft-start time. When enabled, the MAX8819C sequentially ramps up each output. Soft-start eliminates input current surges when regulators are enabled. See the Step-Down Control Scheme section for information about the step-down converters control scheme.
20
Step-Down Input Capacitor The input capacitor in a step-down converter reduces current peaks drawn from the power source and reduces switching noise in the controller. The impedance of the input capacitor at the switching frequency must be less than that of the source impedance of the supply so that high-frequency switching currents do not pass through the input source.
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN
The step-down regulator power inputs are critical discontinuous current paths that require careful bypassing. In the PCB layout, place the step-down converter input bypass capacitors as close as possible to each pair of switching converter power input pins (PV_ to PG_) to minimize parasitic inductance. If making connections to these capacitors through vias, be sure to use multiple vias to ensure that the layout does not insert excess inductance or resistance between the bypass capacitor and the power pins. The input capacitor must meet the input ripple current requirement imposed by the step-down converter. Ceramic capacitors are preferred due to their low ESR and resilience to power-up surge currents. Choose the input capacitor so that its temperature rise due to input ripple-current does not exceed approximately +10C. For a step-down DC-DC converter, the maximum input ripple current is half of the output current. This maximum input ripple current occurs when the step-down converter operates at 50% duty factor (VIN = 2 x VOUT). Bypass each step-down converter input with a 4.7F ceramic capacitor from PV_ to PG_. Use capacitors that maintain their capacitance over temperature and DC bias. Ceramic capacitors with an X7R or X5R temperature characteristic generally perform well. The capacitor voltage rating should be 6.3V or greater.
Step-Down Output Capacitors The output capacitance keeps output ripple small and ensures control-loop stability. The output capacitor must have low impedance at the switching frequency. Ceramic, polymer, and tantalum capacitors are suitable with ceramic exhibiting the lowest ESR and lowest highfrequency impedance. The MAX8819A/MAX8819B require at least 10F of output capacitance. The MAX8819C requires ar least 22F of output capacitance. As the case sizes of ceramic surface-mount capacitors decreases, their capacitance vs. DC bias voltage characteristic becomes poor. Due to this characteristic, it is possible for 0805 capacitors to perform well while 0603 capacitors of the same value may not. The MAX8819A/ MAX8819B require a nominal output capacitance of 10F, however, after their DC bias voltage derating, the output capacitance must be at least 7.5F. Step-Down Inductor Choose the step-down converter inductance to be 4.7H. The minimum recommended saturation current requirement is 700mA. In PWM mode, the peak inductor currents are equal to the load current plus one half of the inductor ripple current. See Table 3 for suggested inductors.
MAX8819A/MAX8819B/MAX8819C
Table 3. Suggested Inductors
MANUFACTURER Sumida Taiyo Yuden TDK TOKO FDK SERIES CDRH2D11HP CDH2D09 NR3012 NR3010 VLF3012 VLF3010 DE2812C MIPF2520 MIPF2016 INDUCTANCE (H) 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 ESR (m) 190 218 130 190 160 240 130 110 160 CURRENT RATING (mA) 750 700 770 750 740 700 880 1100 900 DIMENSIONS (mm) 3.0 x 3.0 x 1.2 = (10.8mm)3 3.0 x 3.0 x 1.0= (9.0mm)3 3.0 x 3.0 x 1.2 = (10.8mm)3 3.0 x 3.0 x 1.0 = (9.0mm)3 2.8 x 2.6 x 1.2 = (8.7mm)3 2.8 x 2.6 x 1.0 = (7.3mm)3 3.0 x 2.8 x 1.2 = (10.8mm)3 2.5 x 2.0 x 1.0 = (5mm)3 2.0 x 1.6 x 1.0 = (3.2mm)3
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN MAX8819A/MAX8819B/MAX8819C
SYS + SYSOK 2.5V RISING 100mV HYST. READY + DT165 +165C DC + DCOVLO 6.0V RISING 400mV HYST. DCPOK + 4.0V RISING 500mV HYST. DCUVLO MAX8819A MAX8819B
DIE TEMP
SOFT-START REG1 EN OK SOFT-START REG2 EN SOFT-START REG3 READY 64 CYCLE DELAY (32s) REGON REGON EN SOFT-START REG4 EN OK REG4OK OK REG3OK OK REG2OK REG1OK
EN123
2MHz OSC BIAS AND REF
EN4
Figure 5a. MAX8819A/MAX8819B Enable/Disable Logic
The peak-to-peak inductor ripple current during PWM operation is calculated as follows: V (V - VOUT ) IP-P = OUT SYS VSYS x fS x L where fS is the 2MHz switching frequency. The peak inductor current during PWM operation is calculated as follows: I IL _ PEAK = ILOAD + P - P 2
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Step-Down Converter Maximum Output Current The maximum regulated output current from a step-down converter is ultimately determined by the p-channel peak current limit (IPK). The calculation follows: IOUT_MAX = IPK - (IP-P/2) For example, if VSYS = 5.3V, VOUT = 3V, fS = 2MHz, L = 4.7H, and IPK = 0.6A:
IP-P = 3V x (5.3V - 3V)/(5.3V x 2MHz x 4.7H) = 0.138A then IOUT_MAX = 0.6A - (0.138A/2) = 0.531A.
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN MAX8819A/MAX8819B/MAX8819C
SYS + SYSOK 2.5V RISING 100mV HYST. READY
MAX8819C
DIE TEMP + DT165 +165C DC + DCOVLO 6.0V RISING 400mV HYST. DCPOK + 4.0V RISING 500mV HYST. EN 2MHz OSC BIAS AND REF EN DCUVLO SOFT-START REG1 OK REG1OK
EN123
SOFT-START REG2 OK REG2OK
SOFT-START REG3 READY 64 CYCLE DELAY (32s) REGON REGON EN SOFT-START REG4 EN OK REG4OK OK REG3OK
EN4
Figure 5b. MAX8819C Enable Logic
As the load current is increased beyond this point, the output voltage sags and the converter goes out of regulation because the inductor current cannot increase above the p-channel peak current limit.
ground. When the short is removed, the inductor current raises the voltage on the output capacitor and the stepdown converter resumes normal operation.
Step-Down Converter Short-Circuit Protection The step-down converter implements short-circuit protection by monitoring the feedback voltage, VFB_. After softstart, if VFB_ drops below 0.23V, the converter reduces its switching frequency to fS/3. The inductor current still reaches the p-channel peak current limit, however, at one-third the frequency. Therefore, the output and input currents are reduced to approximately one-third of the maximum value in response to an output short circuit to
REG1 Reset (RST1) RST1 is an active-low, open-drain output that pulls low to indicate that FB1 is below its regulation threshold. RST1 goes high 200ms after FB1 reaches its regulation threshold. RST1 is high-impedance when EN123 is high. See Figures 6 and 7. A 50s blanking delay is provided when FB1 is falling, so that RST1 does not glitch if the REG1 output voltage is dynamically adjusted by altering the resistors in its feedback network.
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN MAX8819A/MAX8819B/MAX8819C
NOTES 1 2 3 4 5 6 7 8
VDC VBAT < VSYS < VDC VSYS VBAT tSS-D-S VEN123 VBAT
VOUT1
tSS1
VOUT2
tSS2
VOUT3
tSS3
HIGH IMPEDANCE
VRST1 tDRST VEN4
VOUT4
VSYS - VD
tSS4
VSYS - VD
VCEN
VCHG
tSS_CHG
Figure 6. MAX8819A/MAX8819B Enable/Disable Waveforms Example
Step-Down Converter Active Discharge in Shutdown Each MAX8819_ step-down converter (REG1, REG2, REG3) has an internal 1k resistor that discharges the output capacitor when the converter is off. The discharge resistors ensure that the load circuitry powers down completely. The internal discharge resistors are connected when a converter is disabled and when the device is in UVLO with an input voltage greater than 1.0V. With an input voltage less than 1.0V the internal discharge resistors are not activated. Step-Down Converter Enable/ Disable (EN123) and Sequencing Figure 5a shows the MAX8819A/MAX8819B enable and disable logic. Figure 5b shows the MAX8819C
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enable/disable logic. Figure 6 shows an example of enable and disable waveforms for the MAX8819A/ MAX8819B. Figure 6 notes: 1) The device is off with no external power applied to DC. The system voltage (VSYS) is equal to the battery voltage (VBAT). 2) An external supply is applied to DC that causes the step-down converter to power up after the DC-toSYS soft-start time (tSS-D-S). When the DC input is valid and DLIM[1:2] 11, VSYS increases. 3) When V1 reaches the reset trip threshold (VTHRST), the reset deassert delay timer starts. When the reset deassert delay timer expires (tDRST1), RST1 goes high-impedance. If RST1 is connected to the RESET
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN MAX8819A/MAX8819B/MAX8819C
NOTES 1 2 3 4 5 6 7
VDC VBAT < VSYS < VDC VSYS VBAT tSS-D-S VEN123 VBAT
VOUT3
tSS3
VOUT2
tSS2
VOUT1
tSS1 HIGH IMPEDANCE
VRST1 tDRST VEN4
VOUT4
VSYS - VD
tSS4
VSYS - VD
VCEN
VCHG tSS_CHG
Figure 7. MAX8819C Enable/Disable Waveforms Example
input of the system P, the processor can begin its boot-up sequence up at this time. 4) During the P's boot-up sequence, it asserts EN123 to keep the step-down converters enabled, even if DC is removed. 5) After the P has booted, it asserts EN4 to turn on the display's backlight. 6) CEN is asserted by the P to start a charge cycle. 7) The external supply is removed from DC and VSYS falls. The converters remain enabled because the P has asserted EN123 and EN4, but the battery charging current drops to zero even though CEN is still asserted. CHG goes high impedance. 8) System is turned off by deasserting EN123, EN4, and CEN; RST1 goes low to reset the P.
Figure 7 notes: 1) The MAX8819C is off with no external power applied to DC. The system voltage (VSYS) is equal to the battery voltage (VBAT). 2) An external supply is applied to DC that causes the step-down regulator to power up after the DC-toSYS soft-start time (tSS-D-S). When the DC input is valid and DC is not suspended, VSYS rises. 3) EN123 is pulled high to start the OUT3, OUT2, and OUT1 power-up sequence. When OUT1 reaches the reset trip threshold (V THRST ), the reset deassert delay timer starts. When the reset deassert delay timer expires (tDRST1 200ms typ.), RST1 goes highimpedance. If RST1 is connected to the RESET input of the system P, the processor can begin its bootup sequence at this time.
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN MAX8819A/MAX8819B/MAX8819C
4) EN4 to turn on the display's backlight. 5) CEN is asserted by the P to start a charge cycle. 6) The external supply is removed from DC and VSYS falls. The regulators remain enabled because EN123 and EN4 are asserted, but the battery charging current drops to zero even though CEN is still asserted. CHG goes high-impedance. 7) System is turned off by deasserting EN123, EN4, and CEN. OUT1, OUT2, and OUT3 power down in the opposite order of power-up. RST1 goes low to reset the P. 1MHz switching frequency allows for tiny external components. The step-up converter control scheme optimizes the efficiency while achieving low EMI and low input ripple. If the step-up converter (REG4) is not needed, disable REG4 by grounding EN4, LX4, PG4, and OVP4. COMP4 can be unconnected.
Step-Up Converter (REG4)
The step-up converter (REG4) operates by regulating the voltage at FB4 to 0.5V. REG4 operates from the system voltage (VSYS); this voltage can vary from 2.6V to 4.35V (MAX8819A/MAX8819C) or 5.3V (MAX8819B). The
REG4 WLED Driver Configuration Figure 1 shows that REG4 is configured as a white light emitting diodes (WLED) driver, typically used to drive up to six devices with an output voltage up to 24V. The full-scale current is set by resistor R1, according to the following relationship: V IFS = FB4 , where VFB4 = 0.5V no min ally R1 IFS < 0.5V / 16 = 30.9mA
28 29 30 31 32 33
STEP EN4
0
1
2
3
4
5
tHI_INIT > 100s tHI tSOFT-START tLO FULL 31/32 500ns TO 500s 30/32 29/32 28/32 27/32 6/32 SHUTDOWN 5/32 > 500ns FULL 31/32 tSHDN 2ms (typ)
ILED
4/32
3/32
2/32
1/32
SHUTDOWN
Figure 8. Dimming Control Timing Diagram
Table 4. REG4 Recommended Inductors
MANUFACTURER TOKO FDK SERIES DE2812C DB3018C MIP3226 INDUCTANCE (H) 10 10 10 ESR (m) 290 240 160 CURRENT RATING (mA) 580 630 900 DIMENSIONS (mm) 3.0 x 2.8 x 1.2 = (10.8mm)3 3.2 x 3.2 x 1.8 = (18.4mm)3 3.2 x 2.6 x 1 = (8.32mm)3
Table 5. REG4 Recommended Diodes
MANUFACTURER PART NUMBER CMDSH05-4 CMHSH5-4 PMEG3005EB MBR0530L CONTINUOUS CURRENT (mA) 500 500 500 500 FORWARD VOLTAGE (mV) 470 510 500 430 BREAKDOWN VOLTAGE (V) 40 40 30 30 PACKAGE SOD-323 SOD-123 SOD-523 SOD-123
Central Semiconductor NXP ON Semiconductor
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN
EN4 enables REG4, disables REG4, and adjusts the voltage on FB4 in 32 linear steps. If current adjustment is not required, EN4 acts as a simple enable/disable controller. Driving EN4 high for at least 100s powers up REG4 and sets VFB4 to 0.5V. Pulling EN4 low for at least 2ms disables REG4. To adjust VFB4, apply pulses as shown in Figure 8. Dim the WLEDs by pulsing EN4 low (500ns to 500s pulse width). Each pulse reduces the LED current by 1/32. Note: When REG4 is disabled, OUT4 is equal to VSYS minus the drop from the catch diode. In the event that the load (typically WLEDs) opens, VOUT4 rises quickly until it reaches the overvoltage protection threshold (typically 25V). When this occurs, REG4 stops switching and latches off until EN4 is reset low for at least 2ms.
Soft-Start/Inrush Current
The MAX8819_ implements soft-start on many levels to control inrush current to avoid collapsing supply voltages, and to fully comply with the USB 2.0 specifications. All DC and charging functions implement soft-start. The DC node only requires 4.7F of input capacitance. Furthermore, all regulators implement soft-start to avoid transient overload of power inputs.
MAX8819A/MAX8819B/MAX8819C
Undervoltage and Overvoltage Conditions
DC UVLO DC undervoltage lockout (UVLO) prevents an input supply from being used when its voltage is below the operating range. When the voltage from DC to GND (VDC) is less than the DC UVLO threshold (4.0V, typ), the DC input is disconnected from SYS, the battery charger is disabled and CHG is high impedance. BAT is connected to SYS through the internal system load switch in DC UVLO mode, allowing the battery to power the SYS node. REG1-REG4 and the LED current sinks are allowed to operate from the battery in DC UVLO mode. DC OVLO DC overvoltage lockout (OVLO) is a fail-safe mechanism and prevents an input supply from being used when its voltage exceeds the operating range. The absolute maximum ratings state that DC withstands voltages up to 6V. Systems must be designed so that DC never exceeds 6V (transient and steady-state). If the voltage from DC to GND (VDC) should exceed the DC OVLO threshold (5.9V typ) during a fault, the DC input is disconnected from SYS, the battery charger is disabled, and CHG is high impedance. BAT is connected to SYS through the internal system load switch in DC OVLO mode, allowing the battery to power SYS through the internal system load switch in DC OVLO mode. REG1-REG4 are allowed to operate from the battery in DC OVLO mode. Normal operation resumes when VDC falls within its normal operating range. SYS UVLO SYS undervoltage lockout (UVLO) prevents the regulators from being used when the input voltage is below the operating range. When the voltage from SYS to GND (VSYS) is less than the SYS UVLO threshold (2.5V, typ), REG1-REG4, the LED current sinks, and the battery charger are disabled. Additionally, CHG, is high impedance and RST1 is asserted.
Step-Up Converter Inductor Selection The WLED boost converter switches at 1MHz, allowing the use of a small inductor. A 10H inductance value is recommended for most applications. Smaller inductances require less PCB space.
Use inductors with a ferrite core or equivalent. Powdered iron cores are not recommended for use at high-switching frequencies. The inductor's saturation current rating should preferably exceed the REG4 n-channel current limit of 700mA. Choose an inductor with a DC resistance less than 300m to maintain high efficiency. Table 4 lists recommended inductors.
Step-Up Converter Diode Selection The REG4 diode must be fast enough to support the switching frequency (1MHz). Schottky diodes, such as Central Semiconductor's CMHSH5-4 or ON Semiconductor's MBR0530L, are recommended. Make sure that the diode's peak-current rating matches or exceeds the 700mA REG4 n-channel current limit. The diode's average current rating should match or exceed the output current. The diode's reverse breakdown voltage must exceed the voltage from the converter's output to ground. Schottky diodes are preferred due to their low forward voltage, however, ultra high-speed silicon rectifiers are also acceptable. Step-Up Converter Output Capacitor Selection For most applications, a 0.1F ceramic output filter capacitor is suitable. Choose a voltage rating double the maximum output voltage to minimize the effect of the voltage coefficient on decreasing the effective capacitance. To ensure stability over a wide temperature range, ceramic capacitors with an X5R or X7R dielectric are recommended. Place these capacitors as close as possible to the IC.
Thermal Limiting and Overload Protection
Smart Power Selector Thermal-Overload Protection The IC reduces the DC current limit by 5%/C when the die temperature exceeds +100C. The system load (ISYS) has priority over the charger current, so input
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN MAX8819A/MAX8819B/MAX8819C
OUT_
GATE DRIVE TO SWITCH 3.3V V1 3V 3.35V 500mV/div 3V 4.2V 2V/div 5V/div 0V
RT FB_ RB
RD
RST1
100s/div
Figure 9. Dynamic Output Voltage Control
Figure 10. Dynamic Voltage Adjustment with Example Values
current is first reduced by lowering charge current. If the junction temperature still reaches +120C in spite of charge current reduction, no input current is drawn from DC; the battery supplies the entire load and SYS is regulated 70mV below BAT.
RD is calculated using the higher set voltage and the following equations assuming the switch resistance is negligible: RT VOUTH -1 VFB 1 RD = 1 1 - RPAR RB RPAR = where RPAR is the parallel resistance of RB and RD, VOUTH is the higher set voltage, and VFB is the feedback regulation voltage, 1V (typ). For example, if V OUTL = 3V, V OUTH = 3.3V, R B = 100k, then: RT = 100k x ((3V/1V) - 1) = 200k RPAR = 200k/((3.3V/1V) - 1) = 86.96k RD = 1/((1/86.96k) - (1/100k)) = 666.7k Choose RD = 665k as the closest standard 1% value. CH1 = gate drive to switch CH2 = V1, 1V offset; 3V to 3.3V to 3V, 10 load CH3 = RST1 The scope plot (Figure 10) shows V1 switching from 3V to 3.3V to 3V with the resistor values of the example. When the switch is turned on, V1 slews from 3V to 3.3V in about 20s, which is less than the 50s RST1 deglitch filter, and therefore, RST1 does not trip. When the switch is turned off, V1 soars to about 3.35V due to the energy in the inductor. Since V1 is above the regulation voltage, REG1 skips until V1 decays to the regulation voltage. The decay rate is determined by the output capacitance and the load. In this example, the output capacitance is 10F and the load is 10, so the time
Regulator Thermal-Overload Shutdown The IC disables all regulator outputs and the battery charger when the junction temperature rises above +165C, allowing the device to cool. When the junction temperature cools by approximately 15C the regulators and charger resume the state indicated by the enable input (EN123, EN4, and CEN) by repeating their soft-start sequence. Please note that this thermal-overload shutdown is a fail-safe mechanism; proper thermal design should ensure that the junction temperature of the MAX8819_ never exceeds the absolute maximum rating of +150C.
Applications Information
Dynamic Output Voltage Adjustment for Step-Down Converters
Dynamic output voltage adjustment can be implemented for the step-down converter by adding a resistor and a switch from FB_ to GND. See Figure 9. To calculate the resistor-divider, start with the lower voltage desired and calculate the resistor-divider using RT and RB only. Setting RB = 100k is acceptable. Use the following equation to calculate RT: V RT = RB x OUTL - 1 VFB where VOUTL is the desired lower output voltage and VFB is the feedback regulation voltage, 1V (typ).
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PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN
constant is R x C = 100s, and the output voltage decays to within 1% of final value in about 500s.
MAX8819A/MAX8819B/MAX8819C
PCB Layout and Routing
Good printed circuit board (PCB) layout is necessary to achieve optimal performance. Refer to the MAX8819A Evaluation Kit for Maxim's recommended layout. Use the following guidelines for the best results: * The LX_ rapidly switches between PV_ and PG_. Minimize stray capacitance on LX_ to maintain high efficiency. * Keep the FB_ node away from noise sources such as the inductor. * The exposed pad (EP) is the main path for heat to exit the IC. Connect EP to the ground plane with thermal vias to allow heat to dissipate from the device. * Use short and wide traces for high-current and discontinuous current paths. * The step-down converter power inputs are critical discontinuous current paths that require careful bypassing. Place the step-down converter input bypass capacitor as close as possible to the PV_ and PG_ pins. * Minimize the area of the loops formed by the stepdown converters' dynamic switching currents.
8819_ETI TIyww + aaaa
Figure 11. Package Marking Example
Pin Configuration
PV13 CHG 15 14 13 12 CISET FB1 CEN DC SYS BAT RST1 11 10 9 EXPOSED PAD (EP) 1 COMP4 2 FB4 3 OVP4 4 PG4 5 LX4 6 GND 7 EN4 8 PG3 PG1 16 LX3 LX1 17
TOP VIEW
21 FB2 22 FB3 23 EN123 24 PV2 25 LX2 26 PG2 27 DLIM2 28 +
DLIM1
20
19
18
MAX8819A MAX8819B MAX8819C
Package Marking
The top of the MAX8819_ package is laser etched as shown in Figure 11: "8819_ETI" is the product identification code. The full part number is MAX8819_ETI; however, in this case, the "MAX" prefix is omitted due to space limitations. The "_" corresponds to the "A" or "B" version. "yww" is a date code. "y" is the last number in the Gregorian calendar year. "ww" is the week number in the Gregorian calendar. For example: * "801" is the first week of 2008; the week of January 1st, 2008. * "052" is the fifty-second week of 2010; the week of December 27th, 2010. * "aaaa" is an assembly code and lot code. * "+" denotes lead-free packaging and marks the pin 1 location.
Chip Information
PROCESS: S45T
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 28 TQFN-EP PACKAGE CODE T2844+1 DOCUMENT NO. 21-0139
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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